The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 1999

Filed:

Jul. 05, 1996
Applicant:
Inventors:

Yasushi Shizuki, Ichikawa, JP;

Yuji Iseki, Yokohama, JP;

Naoko Ono, Tokyo, JP;

Kunio Yoshihara, Yokohama, JP;

Masayuki Saito, Yokohama, JP;

Hiroshi Yamada, Yokohama, JP;

Kazuki Tateyama, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257778 ; 257779 ; 257780 ; 257786 ;
Abstract

A semiconductor device includes a wiring board having a main surface and a plurality of pad electrodes formed on the main surface, a rectangular semiconductor element having a main surface facing the main surface of the wiring board and mounted on the main surface of the wiring board, a solder resist formed to surround the semiconductor element with a preset distance therefrom on the main surface of the wiring board, a plurality of terminal electrodes formed on the end portion of the main surface of the semiconductor element, and a plurality of solder bumps for electrically connecting the plurality of pad electrodes to the plurality of terminal electrodes with a gap provided between the main surface of the wiring board and the main surface of the semiconductor element, wherein each of the plurality of pad electrodes includes at least a portion which extends from substantially under a corresponding one of the plurality of terminal electrodes of the semiconductor element to the solder resist lying outside the semiconductor element and each of the plurality of solder bumps includes a portion extending over part of a corresponding one of the plurality of pads which lies outside the semiconductor element.


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