High-throughput interconnect allowing bus transactions based on partial

Abstract

A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.