The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 1999
Filed:
Jun. 03, 1997
Takeshi Onishi, Gyoda, JP;
Katsuhiko Suzuki, Saitama, JP;
Advantest Corporation, Tokyo, JP;
Abstract
A semiconductor device testing apparatus in which ICs to be tested are loaded on a test tray in a loader section, the test tray is transported into a test section to test the ICs, after the completion of the test, the tested ICs on the test tray are transferred from the test tray onto a general-purpose tray in an unloader section, the test tray which has been emptied of the tested ICs is transported to the loader section, and the above operation is repeated, and which can detect a failure of an IC carrier mounted to the test tray independently of detection of a failure IC socket is provided. An IC carrier failure analysis memory is provided which has storage addresses the number of which is equal to the number of IC carriers mounted to each of the test trays, and the number of ICs as determined to be defective is stored and accumulated in each of the storage addresses of the IC carrier failure analysis memory. When the accumulated value exceeds a setting value, a decision is rendered that the associated IC carrier on which the ICs as determined to be defective have been loaded is defective.