Timing control for a matrixed scanned array

Abstract

A matrix display maintains synchronization with an input NTSC composite video signal by combining the functions of a phase locked loop, a column selector, and a row selector. The matrix includes display cells arranged in rows and columns, each display cell enabled for display on receipt of a column pointer signal and a row pointer signal. The column selector includes a shift circuit that shifts a walking-one pattern to assert in turn one column pointer signal at a time for each column in the matrix. An overflow signal from the shift circuit is used for three functions: (1) to reinstate the walking pattern in the column selector, (2) to lock the phase locked loop on the horizontal synchronization pulse of the NTSC signal, (3) to clock the row selector. The row selector includes a shift circuit and walking-one pattern to assert in turn one row pointer signal for each row of the matrix. Vertical synchronization is maintained by recording several samples of the NTSC signal taken after successive horizontal synchronization pulses, and selectively disabling the phase comparator of the phase locked loop. In a preferred embodiment, the matrix display includes field emission display cells arranged with all support circuitry on an integrated circuit substrate. Shift circuits, consisting of low power dynamic shift stages, eliminate conventional counter circuitry saving surface area on the substrate and reducing heat and power consumption.