The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 1999

Filed:

Jan. 31, 1997
Applicant:
Inventors:

Somit Talwar, Palo Alto, CA (US);

Karl-Josef Kramer, Menlo Park, CA (US);

Guarav Verma, Palo Alto, CA (US);

Kurt Weiner, San Jose, CA (US);

Assignee:

Ultratech Stepper, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438199 ; 438486 ; 438487 ; 438483 ; 438508 ; 438530 ; 438542 ; 438557 ; 438575 ; 148D / ;
Abstract

Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.


Find Patent Forward Citations

Talwar, Somit. (1999). Fabrication method for reduced-dimension fet devices (U.S. Patent No. 5908307). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5908307

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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