The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 1999
Filed:
Feb. 26, 1997
Haruo Iwasaki, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
The invention relates to the fabrication of a cylindrical storage node in a stacked capacitor cell of DRAM. As is usual, a MOS transistor is fabricated in a silicon substrate, and interlayer insulator and interconnection are formed on the substrate. As an upper interlayer insulator film which serves as an etch stop film, a silicon nitride or silicon oxide film is formed, and this film is overlaid with a planarizing film such as a BPSG film. Then, a contact hole is formed and filled with a conductor to provide a storage node contact. After that the planarizing film is removed, and a cylindrical storage node is formed on the exposed etch stop film. The cylindrical part of the storage node is formed by patterning a relatively thick BPSG film so as to provide a cylindrical wall face, forming a polysilicon sidewall on the cylindrical wall face and then completely removing the BPSG film. At this stage the etch stop film retains sufficient thickness since this film was protected by the planarizing film at the stage of forming the storage node contact. So, no defects such as cavities develop in interlayer insulators. By this method the total thickness of interlayer insulators can be reduced, so that the storage node contact can be formed accurately and reliably.