The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 1999

Filed:

Dec. 04, 1997
Applicant:
Inventors:

David R Evans, Beaverton, OR (US);

Sheng Teng Hsu, Camas, WA (US);

Jong Jan Lee, Camas, WA (US);

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438-3 ; 438240 ; 438253 ;
Abstract

A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.


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