The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 1999
Filed:
Jul. 30, 1996
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the special purpose FPGA, inter-FPGA, inter-logic boards, and inter-backplanes. More specifically, under the presently preferred embodiment, an on-chip 3-stage inter-logic element crossbar network is provided to each special purpose FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the special purpose FPGA. A two level three-stage inter-FPGA hybrid crossbar network is provided to interconnect the special purpose FPGAs and I/O pins of the logic board. The two-level three-stage inter-FPGA hybrid crossbar network consists of two stages of programmable crossbars and one stage of one or more special purpose FPGAs used for interconnection only. The exact number of special purpose FPGAs to be used for interconnection only on a particular logic board is dependent on the specific circuit design being emulated. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.