The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 1999

Filed:

Apr. 11, 1997
Applicant:
Inventors:

Wai Keung Tsang, Elk Grove, CA (US);

Harry Q Pon, Sacramento, CA (US);

Robert E Larsen, Shingle Springs, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518905 ; 326 26 ; 326 27 ; 327108 ; 327112 ;
Abstract

A high-speed output buffer for a nonvolatile writeable memory is described. The high-speed output buffer receives signals from the nonvolatile writeable memory having a pair of logic levels. The high-speed output buffer provides output signals having a pair of logic levels that may differ from the pair of logic levels of the signal received from the nonvolatile writeable memory. The high-speed output buffer comprises two inverters, a pull-up device, and a circuit with a relatively low voltage drop. The circuit with the relatively low voltage drop causes the high-speed output buffer to receive signals having one pair of logic levels while providing high-speed output signals having another pair of logic levels which may differ from the pair of logic levels of the received signal. The high-speed output buffer is coupled to a different power supply output from the nonvolatile writeable memory. The high-speed output buffer uses input and output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.


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