Method and apparatus for dynamic control of clocks in a multiple clock

Abstract

A method and apparatus are provided for controlling clocks for a processor and L2 cache. The clock signal to an L2 cache may be shut down in order to conserve power. Due to the nature of CMOS circuitry typically comprising the SRAM in an L2 cache, shutting down the clock signal to the L2 cache may significantly reduce the amount of power consumed by the L2 cache. A clock control circuitry may be provided to generate and control clock signals to a processor (e.g., Pentium.RTM. processor) and an L2 cache. Controllable clock skew adjustment may be provided to adjust relative timing between clock signals. Skew adjustment for the L2 cache clock may be provided with an AND gate for interrupting the clock signal. The AND gate may be controlled by one of a number of signals indicating status of the L2 cache. Address strobe, L2 idle, or pipelining conditions may determine whether the clock signal to the L2 cache may be interrupted. The use of combinational logic circuitry allows for seamless shutdown and restarting of the L2 cache clock signal. The present invention has particular application to a system where interface circuits may be used to interface a Pentium.RTM. processor to a VL bus.