The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 1999
Filed:
May. 27, 1998
Sameer S Haddad, San Jose, CA (US);
Wing H Leung, Cupertino, CA (US);
John Chen, Cupertino, CA (US);
Ravi S Sunkavalli, Santa Clara, CA (US);
Ravi P Gutala, Milpitas, CA (US);
Jonathan S Su, Evanston, IL (US);
Colin S Bill, Cupertino, CA (US);
Vei-Han Chen, San Jose, CA (US);
Advanced Micro Devices, Sunnyvale, CA (US);
Abstract
A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or 'soft programming' pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.