Skewed memory cell apparatus and method

Abstract

An improved random-access memory apparatus and method for rapidly reading and writing high-level logic data to and fiom the random-access memory apparatus during phase-driven timing cycles. The improved random-access memory apparatus includes an unbalanced storage circuit for the evanescent storage of binary data, and includes two opposing logic inverters coupled together such that high level logic data can be rapidly written to the unbalanced storage circuit during a write cycle. A first logic inverter is sized larger than a second logic inverter. In addition, the improved random-access memory apparatus includes a circuit for reading and writing binary data to and from the unbalanced storage circuit. The circuit for reading and writing binary data to and from the unbalanced storage circuit operates in a cycle which includes clock phases carried on a phase line to the circuit for reading and writing binary data to and from the unbalanced storage circuit. The first logic inverter included within the unbalanced storage circuit is preferably a high-performance type of logic inverter type and the second logic inverter is preferably of a type weak in its ability to drive a binary logic signal. The unbalanced storage circuit preferably operates in a cycle which includes four clock phases carried on the phase line to the circuit for reading and writing binary data to and from the unbalanced storage circuit.