The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 1999
Filed:
Mar. 03, 1997
Alfred J Reich, Austin, TX (US);
Kevin D Lucas, Austin, TX (US);
Michael E Kling, Austin, TX (US);
Warren D Grobman, Austin, TX (US);
Bernard J Roman, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the elements within the circuit design. When this is not the case, the exposure radiation behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the designs themselves can be altered so that the final printed results better match the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Edge assist shapes and edge biasing features are added to integrated circuit designs by shape manipulation functions to perform one dimensional (1-D) LPC.