Mutual exclusivity circuit for use in test pattern application scan

Abstract

A circuit for locally ensuring mutual exclusivity of selected signals during scan testing is coupled between an IEEE 1149.1 TAP controller and a conventional gating circuit. The mutual exclusivity circuit includes an AND-gate, an inverter, a first scan flip-flop and a second scan flip-flop. The first and second flip-flops have their scan-input leads hardwired to receive logic '1' and logic '0' signals, respectively. The first flip-flop also has its data input lead hardwired to receive a logic '0' signal. During the scan mode, the AND-gate receives a conventional rst.sub.-- tri.sub.-- en signal from the TAP controller. Thus, the AND-gate outputs a local.sub.-- rst.sub.-- tri.sub.-- en signal identical to the rst.sub.-- tri.sub.-- en signal. After the test pattern is scanned in, the rst.sub.-- tri.sub.-- en signal transitions to a logic '1' level, causing the local.sub.-- rst.sub.-- tri.sub.-- en signal to transition to a logic high level, which allows the test pattern to propagate through the circuit under test. At the leading edge of the capture pulse, the circuit enters the normal functional mode in which the second flip-flop stores and outputs the logic '1' signal outputted by the first flip-flop. After the propagation delay from the second flip-flop and the inverter, this logic '1' signal is inverted, causing the AND-gate to output the local.sub.-- rst.sub.-- tri.sub.-- en signal at a logic '0' level. This propagation delay is predetermined to allow the response data to be captured in the scan chain without damaging the circuit device requiring mutually exclusive signals, thereby removing the response data constraint on the test pattern.