The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1999
Filed:
Oct. 16, 1991
Gary N Hammond, Campbell, CA (US);
Pradeep Dubey, White Plains, NY (US);
Mustafiz R Choudhury, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a descriptor cache such that the association between the descriptors is indicated. Whenever a descriptor in the data cache with a set inclusion bit is altered, the entire descriptor cache is flushed by virtue of the set inclusion bit. Furthermore, in the same embodiment, a valid bit is set for a descriptor in the data cache which is cached from the descriptor table. Whenever a descriptor in the descriptor table, which has a valid bit set in the data cache, is modified, the valid bit is reset. And if the same descriptor with its valid bit reset has a set inclusion bit, then the entire descriptor cache is flushed. As a result, the cache coherency among descriptor cache, data cache and descriptor table is preserved in this improved memory management system.