The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 1999

Filed:

Mar. 20, 1997
Applicant:
Inventors:

Yasunori Inoue, Ohgaki, JP;

Kazutoshi Tsujimura, Ohgaki, JP;

Shinichi Tanimoto, Ohgaki, JP;

Yasuhiko Yamashita, Hashima, JP;

Kiyoshi Yoneda, Gifu-ken, JP;

Yoshikazu Ibara, Gifu-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438643 ; 438660 ; 438669 ; 438688 ; 438658 ;
Abstract

A semiconductor device includes an insulating layer and an interconnection layer having a conductive layer provided over the insulating layer. The interconnection layer is patterned by photolithography. The device further includes a cap-metal layer, which is deposited on the conductive layer and suppresses reflection of light beams at the time of patterning the interconnection layer. The cap-metal layer has any one of the following structures: a double-layered structure having a titanium nitride layer and a titanium layer located between the titanium nitride layer and the conductive layer; a double-layered structure having a titanium nitride layer and an aluminum-titanium alloy layer located between the titanium nitride layer and the conductive layer; and a single-layered structure consisting essentially of an aluminum-titanium alloy. These design ensure accurate interconnection patterning in the photolithography, and provide improved EM and SM immunities of the interconnection.


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