The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1999
Filed:
May. 15, 1996
Advanced Micro Devices, Inc., , US;
Abstract
A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique. Following deposition of the dopant-rich oxide layer, the silicon wafer is heated to drive dopant atoms from the dopant-rich oxide layer into the underlying polysilicon layer, and to electrically activate the dopant atoms within the polysilicon layer. The presence of electrically active dopant atoms within the polysilicon layer lowers the electrical resistivity of the polysilicon layer. After the heating step, the dopant-rich oxide layer is removed.