Method of forming semicrown-shaped stacked capacitors for dynamic random

Abstract

A method for making semicrown stacked capacitors for DRAM devices is achieved. A first insulating layer, a second insulating etch-stop layer, and a high-etch-rate third insulating layer are sequentially formed on a substrate over the memory cell areas having FETs with source/drain areas. Recesses are etched in the third and second insulating layers for bottom electrodes, aligned over device areas. Node contact openings are plasma etched in the first insulating layer exposed in the recesses to one of each source/drain area. A first polysilicon layer is deposited to form node contacts and the bottom electrodes. A high-etch-rate fourth insulating layer is used to fill the recesses. The fourth insulating layer and the first polysilicon layer are etched or chem/mech polished back to form the array of bottom electrodes having oxide plugs. The plugs and third insulating layer are wet etched to the etch-stop layer to form the semicrown bottom electrodes. A thin dielectric layer is deposited, and a patterned second polysilicon layer is formed for top electrodes. The etch-stop layer, retained in the final structure, supports the bottom electrodes to reduce mechanical damage during subsequent processing and to also reduce the nonuniformity across the substrate for an improved photolithographic process window.