The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1999
Filed:
Jun. 17, 1997
Ian Robert Harvey, Livermore, CA (US);
Xi-Wei Lin, Fremont, CA (US);
Ramiro Solis, Bandera, TX (US);
VLSI Technology, Inc., Mountain View, CA (US);
Abstract
A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface. As a result, the source and drain diffusion regions of the semiconductor substrate and the top surface of the polysilicon gate are prepared for subsequent silicide formation therein.