Integrated circuit tester with distributed instruction processing

Abstract

An integrated circuit (IC) tester includes a master controller and a set of tester nodes. Each tester node includes a vector memory controller, a vector memory, and a pin electronics circuit. During a test the pin electronics circuit carries out the sequence of actions in response to a sequence of vectors produced by the vector memory controller. To prepare for a test, a separate set of vectors is written into each vector memory. The vector memory controller thereafter moves blocks of vectors from the vector memory as needed to an internal vector cache. During the test, the master controller sends the same sequence of instructions concurrently to each vector memory controller. Each vector memory controller executes each instruction of the sequence by generating and supplying an address to the vector cache. The vector cache responds by reading out an addressed test vector and supplying it to the pin electronics circuit. Some instructions instruct the vector memory controllers to generate repeating patterns of vector cache addresses so that the read caches produce repeating patterns of output vectors. This enables the tester to perform repetitive portions of a test without drawing additional vectors from the vector memories, thereby reducing the number of vectors that must be distributed thereto.