The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 1999

Filed:

Apr. 29, 1996
Applicant:
Inventors:

H Victor Shadan, Santa Clara, CA (US);

Anurag Nigam, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711205 ; 711206 ; 711207 ; 711108 ; 711128 ; 365 49 ; 36523006 ;
Abstract

A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.


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