Semiconductor integrated circuit device having failure detection

Abstract

A 12.5-MHz signal is applied from outside a semiconductor integrated circuit (SIC) device to a signal input terminal of that SIC device. A frequency multiplying circuit is fed that 12.5-MHz signal from the input terminal, and delivers a reference signal whose frequency is a multiple of the frequency of the signal received (i.e., 100 MHz), to a semiconductor memory and to a self-test circuit. The self-test circuit provides a test signal in synchronism with that 100-MHz reference signal to the semiconductor memory for testing for the presence or absence of a failure. All elements of the semiconductor memory are tested by the self-test circuit for a failure. If the self-test circuit finds a semiconductor memory element that fails to work properly, it provides a signal indicative of such failure to a failure counting circuit. This failure counting circuit counts the number of times the self-test circuit provides such a signal.