The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 1999

Filed:

Jan. 16, 1996
Applicant:
Inventors:

Valery M Dubin, Cupertino, CA (US);

Yosef Shacham-Diamand, Ithaca, NY (US);

Chiu H Ting, Saratoga, CA (US);

Bin Zhao, Austin, TX (US);

Prahalad K Vasudev, Austin, TX (US);

Assignees:

Cornell Research Foundation, Ithaca, NY (US);

Intel Corporation, Santa Clara, CA (US);

Sematech, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B05D / ;
U.S. Cl.
CPC ...
427 98 ; 427305 ; 427355 ; 427427 ; 4274431 ; 438631 ; 438633 ; 438678 ;
Abstract

A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.

Published as:

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