Memory redundancy for high density memory

Abstract

A redundancy architecture suitable for high density mask ROM integrated circuit memory is based on a two transistor redundancy cell that has a very small layout. Both row and column failure modes can be repaired. The redundancy architecture can be manufactured using typical single metal, single polysilicon mask ROM processes. Redundancy cells are based upon a diffusion word line, a redundant word line adapted to replace a word line in the array and spaced away from the diffusion word line. First and second diffusion regions between the diffusion word line and the redundant word line, and a channel region between the first diffusion region and a second diffusion region form part of the redundant cell. A third diffusion region adjacent the redundant word line opposite the second diffusion region is arranged so that the second diffusion region acts as a source terminal, the third diffusion region acts as a drain terminal, and the redundant word line acts as a gate of a transistor. A floating gate member is arranged to overlie a segment of the diffusion word line, and to extend between the diffusion word line and a redundant word line around the first diffusion region and over the channel region between the first diffusion region and the second diffusion region. A first contact is made between the first diffusion region and a first bit line and a second contact is made between a third diffusion region and a second bit line.