The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 1999
Filed:
Apr. 28, 1997
Mosel Vitelic Corporation, San Jose, CA (US);
Abstract
A fuse-programmable circuit controllably enables or disables an electrical signal (S). The circuit includes a transmission gate (118) connected between the circuit's input and output terminals. The transmission gate is controlled by complimentary outputs OUTH, OUTL of a fuse-programmable latch (130). A PMOS transistor (Q41) and a fuse (F41) are connected in series between the output terminal and a power supply voltage (VCC). An NMOS transistor (Q42) and a fuse (F42) are connected in series between the output terminal and a reference voltage (ground). The gate of the PMOS transistor is connected to the latch output OUTH. The gate of the NMOS transistor is connected to the latch output OUTL. When OUTH is high and OUTL is low, the transmission gate couples the signal (S) from the input terminal to the output terminal. When OUTH is low and OUTL is high, the transmission gate is closed. The output terminal is permanently fixed at the power supply voltage level or the reference voltage level depending on which of the two fuses (F41 or F42) is blown and which of the two fuses is intact.