The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 1999
Filed:
Jan. 29, 1997
Somit Talwar, Palo Alto, CA (US);
Guarav Verma, Palo Alto, CA (US);
Karl-Josef Kramer, Menlo Park, CA (US);
Kurt Weiner, San Jose, CA (US);
Ultratech Stepper, Inc., San Jose, CA (US);
Abstract
The method of this invention produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes the steps of producing an amorphous region on the silicon body using ion implantation, for example, forming or positioning a metal such as titanium, cobalt or nickel in contact with the amorphous region, and irradiating the metal with intense light from a laser source, for example, to cause metal atoms to diffuse into the amorphous region. The amorphous region thus becomes an alloy region with the desired silicide composition. Upon cooling after irradiation, the alloy region becomes partially crystalline. To convert the alloy region into a more crystalline form, the invented method preferably includes a step of treating the alloy region using rapid thermal annealing, for example. An insulator layer and a conductive lead can subsequently be patterned to establish electrical contact to the silicide region. The low contact resistivity of the silicide region provides the capability to transmit relatively high-frequency electronic signals through the contact region. In a preferred application, the invented method is used to form self-aligned silicide contact regions for the gate, source and drain of a metal-insulator-semiconductor field-effect transistor (MISFET).