The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 1999

Filed:

Mar. 26, 1998
Applicant:
Inventor:

Ching-Shi Jenq, Los Altos, CA (US);

Assignee:

Integrated Memory Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M / ;
U.S. Cl.
CPC ...
363 60 ; 307110 ; 327537 ;
Abstract

A voltage multiplier has a number of electrically-like stages. Each of the stages receives two input signals and a pump signal. The stage has an MOS transistor with a first source/drain region and a second source/drain region and a gate. Each stage also has means for receiving a pump signal and for separately pumping the first source/drain region and the gate of the first transistor by the pump signal. The two input signals are supplied to the first source/drain region and the gate of the first transistor, respectively. A first output signal is supplied from the second source/drain region of the first transistor, and from the first source/drain region of the first transistor. A voltage signal is supplied as the input signal of the first stage and a clock signal having a first phase is supplied to the first stage as the pump signal of the first stage. The first and second output signals of the first stage are supplied to the second stage as the input signals of the second stage and a clock signal having a second phase different from the first phase is supplied to the second stage as the pump signal of the second stage.


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