Non-blocking multiple phase clocking scheme for dynamic logic

Abstract

A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e., a 'non-blocking') manner so that delay through the dynamic logic circuit can be minimized. To ensure that valid output signals are received by the dynamic logic gates receiving the next clock phase, the clock phases are assigned so that this particular dynamic logic gate receives its input signal(s) before the start of the evaluation phase of any subsequent clock phase.