The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 1999
Filed:
Jan. 31, 1997
Hisashi Matsumoto, Tokyo, JP;
Takio Ohno, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A titanium silicide (4) covers surfaces of P.sup.+ -type diffusion region (7) and N.sup.+ -type diffusion region (8) to electrically connect the diffusion regions (7, 8) through the titanium silicide (4), and a surface of the titanium silicide (4) is covered with an insulation film (10). A power supply potential applied to a metal wire (2) is thereby applied to an N.sup.+ -type diffusion region (6), an N well (12) and the N.sup.+ -type diffusion region (8) through a contact hole (3) and further supplied for the P.sup.+ -type diffusion region (7) serving as a source region of PMOS transistor through the titanium silicide (4). That eliminates the need for providing any contact for supplying the diffusion regions 7 and 8 with the power supply potential to attain reduction in layout size, while preventing a latch-up. Thus, the N well-source structure of a semiconductor integrated circuit device including an SRAM with Full CMOS structure eliminates the need for providing a contact on the surfaces of the P.sup.+ -type diffusion region and the N.sup.+ -type diffusion region, to attain reduction in layout size.