High speed incrementer with array method

Abstract

A high-speed incrementer array for incrementing a data input value by a binary one, wherein the data input value comprises a plurality of input bit values. The incrementer array includes a plurality of word lines, bit-line pairs, and sense amplifiers. The input bit values are received as a plurality of complement input signals and a plurality of true input signals. The complement input signals are transmitted on the plurality of word lines that form the rows of the array. Each one of plurality of bit-line pairs is located in a respective column of the array and is coupled to particular ones of the word lines in the rows of the array. Each one of the plurality of sense amplifiers is coupled to a respective bit-line pair for sensing a voltage difference between the bit-line pair, such that the bit-line pair and the sense amplifier perform a logical NOR of the complement input signals to produce a NOR output. Each one of the plurality of exclusive-or gates is coupled to a respective NOR output and to a particular one of the true input signals for generating an incremented output signal.