The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 1999
Filed:
Jul. 11, 1997
Michio Aruga, Inba-gun, JP;
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
The present invention is a process for planarization of substrate layers comprising apertures to form continuous, void-free contacts or vias in sub-half micron applications. A CVD silicon or metal silicide wetting layer is deposited onto the substrate layer comprising apertures to provide a conformal wetting layer for a PVD metal layer. The PVD metal layer is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The CVD layer diffuses into the PVD layer and the resulting conductive layer is substantially void-free. The planarization process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of vias and contacts occurs without the formation of an oxide layer over the CVD wetting layer.