The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 1999
Filed:
Dec. 22, 1995
Robert N Hasbun, Shingle Springs, CA (US);
Daniel H Leemann, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method of accessing a memory includes the step of partitioning the memory into a plurality of partitions. A primary logical identifier is stored in the memory to identify each partition. A redundant secondary logical identifier is also stored in the memory to identify each partition. In response to a requested partition number identifying a partition to access, at least one partition of data is located using a first stored logical identifier formed from a portion of each of the primary and secondary logical identifiers. The at least one partition of data is then identified using a second stored logical identifier formed from a portion of at least one of the primary and secondary logical identifiers. In one embodiment, a first error detection code (EDC) stored in the header is used to validate the partition data. If an error is detected, the validity of the partition data is tested using an EDC computed by ANDing the first EDC and a second EDC stored in the header. During a clean-up operation, a header is selected from a block targeted for clean-up. The first and second stored logical identifiers in the selected header are compared with each other. If there is not a match, then validation is performed using the ANDed value of the first and second stored logical sector number. In one embodiment, the memory is a flash electrically erasable programmable read only memory. In one embodiment, the partitions are sectors and the identifiers are sector numbers.