The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 1999

Filed:

Sep. 28, 1995
Applicant:
Inventors:

Wen-Doe Su, Chu-Tung, CN;

Chia-Lin Ku, Chu-Pei, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438789 ; 438790 ; 438909 ;
Abstract

A method of fabricating an integrated circuit device with a substantially uniform inter-layer dielectric layer. The method includes steps of providing a partially completed semiconductor wafer (400) where the partially completed semiconductor device has a first polysilicon layer (401) thereon. The method includes depositing a dielectric layer (405) overlying the polysilicon layer and portions of the partially completed semiconductor device at a pressure of about 1 atmosphere. A step of forming a second polysilicon layer overlying portions of the dielectric layer is also included. The dielectric layer depositing step includes combining an organic silane and an ozone at a concentration of 200 g/m.sup.3 and less.


Find Patent Forward Citations

Su, Wen-Doe. (1999). Method for forming insulating layers between polysilicon layers (U.S. Patent No. 5869406). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5869406

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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