Multi-stage interpolating analog-to-digital conversion

Abstract

In a multi-stage, multi-residue interpolating analog-to-digital converter (ADC), which is suitable for pipelined implementation, inputs of at least three amplifiers are 'leapfrog' switched to adjacent nodes of a first interpolation ladder having discrete voltage levels established thereon. Pairs of the amplifiers drive second interpolation ladders to establish additional discrete voltage levels (in a nominal and an overlap conversion region) at nodes of the second interpolation ladders. A bank of comparators compares a predetermined threshold voltage, e.g., ground, to several of the discrete voltage levels at the nodes of the first interpolation ladder. The switches controlling which inputs of the amplifiers are connected to which nodes of the first interpolation ladder are controlled by a logic circuit which is driven by outputs of the bank of comparators. Alternatively, the bank of comparators compares an input voltage of the ADC to voltage levels established by the first interpolation ladder. In which case, the voltages at the nodes of the interpolation ladder to which the amplifiers are connected are amplified with respect to the input voltage of the ADC.