The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 1999

Filed:

Oct. 08, 1996
Applicant:
Inventors:

Jon A Casey, Poughkeepsie, NY (US);

Michael A Cohn, Ramsey, NJ (US);

John J Garant, Hopewell Junction, NY (US);

Abubaker S Shagan, Fishkill, NY (US);

Candace A Sullivan, Pleasant Valley, NY (US);

Robert J Sullivan, Pleasant Valley, NY (US);

Andrew H Vogel, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438458 ; 156247 ; 156323 ; 156344 ;
Abstract

A process for making multiple microelectronic ceramic substrates uses an interface layer between stacked layers of green sheets that are laminated with the interface layer, then fired to produce the ceramic substrates. The interface layer acts to protect the substrates, and to hold them together before firing, then thermally degrades at a desired point in the firing cycle to separate the individual substrates. The invention also includes the ceramic substrates produced by the method.


Find Patent Forward Citations

Casey, Jon. (1999). Method of using an interface layer for stacked lamination sizing and (U.S. Patent No. 5866470). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5866470

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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