Dynamic random-access memory with high-speed word-line driver circuit

Abstract

A random-access memory includes an array of rows and columns of memory cells. Word lines are associated with rows of memory cells, bit lines lines are with columns of memory cells. A row decoder and a core control circuit are connected to the word lines. A column decoder and a sense amplifier circuit are connected to the bit lines. An individual cell may be addressed by addressing an individual column through a column decoder controlling the voltage on each word line, and through a row decoder controlling the voltage on each word line in response to specified row and column addresses input via row and column address buffers. A booster circuit provides the row decoder with a boosted voltage as a word-line drive voltage. This voltage has been transmitted to a pre-decoder section in the core control circuit before the row address is acquired in the row decoder.