The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 1999

Filed:

Jun. 30, 1997
Applicant:
Inventor:

Tien-Ming Liu, Taoyuan, TW;

Assignee:

Pan Jit International Inc., Kaohsiung Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257544 ;
Abstract

A micro semiconductor bridge rectifier comprises a first and a second diode chips. The first diode chip comprises an N-type substrate on which two P-type regions are formed. The second diode chip comprises a P-type substrate on which two N-type regions are formed. One P-type region of the first diode chip and one N-type region of the second diode chip are connected to one electrode of a first lead frame, the other P-type region of the first diode chip and the other N-type region of the second diode chip are connected to the other electrode of the first lead frame. The N-type substrate of the first diode chip and the P-type substrate of the second diode chip are connected to respective electrodes of a second lead frame. The method for manufacturing the micro semiconductor bridge rectifier comprises the steps of (a) forming the first diode chip, (b) forming the second diode chip, (c) connecting one P-type region of the first diode chip and one N-type region of the second diode chip to one electrode of the first lead frame, and connecting the other P-type region of the first diode chip and the other N-type region of the second diode chip to the other electrode of the first lead frame, and (d) connecting the N-type region of the first diode chip and the P-type region of the second diode chip to electrodes of the second lead frame respectively.


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