Low latency dram cell and method therefor

Abstract

A memory cell and structure are implemented to provide a memory system having the advantages of both static and dynamic memories. A dynamic memory cell is implemented using a capacitor to store charge associated with a data value stored in the cell. The storage capacitor is accessible through multiple switches, and each of the switches is coupled to an independent bitline. Because independent bitlines are implemented, one bitline may sense the data value stored within the memory cell, while a second bitline is pre-charged, or refreshed, for a next memory operation to be performed. Thus, as soon as data is provided to the first bitline, any memory cells sharing the second bitline are ready to be sensed and restored even though they are all in the same data memory array. Such sequential operation is not possible with prior art DRAM memory cells because they require a refresh period in which to pre-charge bitlines accessing the same memory location. By providing the ability to access the same memory cell during a next subsequent timing cycle, a DRAM cell having a very low latency is implemented.