The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 1999

Filed:

Nov. 24, 1997
Applicant:
Inventors:

Teck Koon Lee, Singapore, SG;

Lap Chan, San Francisco, CA (US);

Chock H Gan, Singapore, SG;

Po-Ching Liu, Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
438291 ; 438299 ; 438592 ;
Abstract

A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.


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