The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 1999
Filed:
Mar. 23, 1998
Yau-Kae Sheu, Hsinchu, TW;
United Semiconductor Corp., Hsinchu, TW;
Abstract
A method of fabricating split-gate slash memory can define source and drain regions by using a self-alignment process. Thus, the uniformity of the split-gate flash memory performance is better controlled. This method comprises a floating gate oxide layer, a first polysilicon layer and a mask layer formed sequentially over a first type substrate. The mask layer and the first polysilicon layer are patterned to form a floating gate. A photoresist layer is coated over the substrate and then a pattern is defined on the photoresist layer to expose portion of the substrate. Second type ions are implanted into the exposed substrate to form a drain region. Then, the photoresist layer is removed. An insulating layer is formed over the substrate and then is etched back to form spacers on one side of the floating gate. The second type ions are implanted into the substrate to form a source region. The spacers and the mask layer are removed. A control gate layer and a control gate are formed sequentially over the substrate.