The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 1999

Filed:

Oct. 03, 1995
Applicant:
Inventors:

Satoru Takada, San Mateo, CA (US);

Hidetoshi Inoue, Cupertino, CA (US);

Yoshihiro Hara, Nishi-ku, JP;

Assignee:

Kobe Precision, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23F / ;
U.S. Cl.
CPC ...
1566361 ; 1566451 ; 216 88 ; 216 89 ; 437228 ;
Abstract

A process comprising removing surface layer materials from the wafer by inducing micro-fractures in the surface using a rotating pad and an abrasive slurry until all of the surface layer materials are removed; and chemically etching the surfaces of the wafer until all micro-fractures are removed therefrom. Edge materials are removed by abrasive tape. Wafer thickness reduction during recycling is less than 30 microns per cycle. One of the front and back surfaces of the wafer substrate is polished, any dots or grooves being on the non-polished side. The abrasive slurry contains more than 6 volume percent abrasive particles, and the abrasive slurry has a viscosity greater than about 2 cP at ambient temperature. The preferred pad comprises an organic polymer having a hardness greater than about 40 on the Shore D scale, optimally a polyurethane. The pressure of the pad against the wafer surface preferably does not exceed about 3 psi. Preferably, the chemical etching solution contains potassium hydroxide. An acidic solution can then be applied to the wafer surface. The reclaimed semiconductor wafer can be a silicon wafer having a matted side having etch pits which does not exceed 20 microns in width, an average roughness not exceeding 0.5 microns and a peak-to-valley roughness not exceeding 5 microns. Any laser markings from the original wafer are present on the matted side of the wafer.


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