The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1998
Filed:
Aug. 05, 1997
Soon-moon Jung, Seongnam, KR;
Yun-seung Shin, Seoul, KR;
Samsung Electronics, Co., Ltd., Suwon, KR;
Abstract
A SRAM cell includes a single line used as both a word line and a power supply voltage line, a first and a second load element, a first and a second NMOS driver transistor, and a first and a second PMOS access transistor. Each of the two load elements is connected between the line and one of two storage nodes. The first load element is connected between the single line and a first storage node. The second load element is connected between the single line and a second storage node. The first NMOS driver transistor is connected between the first storage node and ground. The second driver transistor is connected between the second storage node and ground. The first access transistor is connected between the first storage node and a bit line and the second access transistor is connected between the second storage node and a complementary bit line. The first and second access transistors have gates commonly connected to the single line. The layout of the SRAM cell is simplified and the cell layout area is reduced because a single line is used as both the power supply voltage line and the word line.