The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1998
Filed:
Jul. 07, 1997
Hsiu-Wen Huang, Kaohsiung, TW;
Abstract
The capacitor for a DRAM is formed to have a textured bottom electrode using wet etch processes. A planarized dielectric layer is formed over the transfer FETs and bit line of a capacitor over bit line DRAM cell. A layer of silicon nitride is deposited over the planarized dielectric layer. A layer of silicon oxide is deposited over the silicon nitride layer and then a contact via is etched to expose the charge storage node of a transfer FET of the DRAM cell. A layer of polysilicon is deposited over the silicon oxide layer and into the contact via to connect the polysilicon layer to the charge storage node of the transfer FET. The polysilicon layer is patterned to define bottom capacitor plates. The silicon oxide layer is etched using hydrofluoric acid to expose the bottom surface of the polysilicon bottom capacitor plate. Next, a hydrofluoric acid dip is used to create a rugged polysilicon surface on the upper and lower surfaces of the bottom capacitor electrodes. A capacitor dielectric is provided and an upper capacitor electrode is formed to complete the DRAM cell.