The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1998
Filed:
Jul. 14, 1997
Kwong-Jr Tsai, Chung-Hsung, TW;
Shiang-Peng Cheng, Hsinchu, TW;
Yeur-Luen Tu, Taipei, TW;
Ing-Ruey Liaw, Hsinchu, TW;
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Abstract
A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.