The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 1998

Filed:

Jul. 24, 1997
Applicant:
Inventor:

Donald J Coleman, Jr, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365210 ; 365203 ; 365205 ; 365206 ;
Abstract

A memory array (10) implemented by an integrated circuit is provided. The memory array (10) includes a bank of standard array cells (12) arranged in rows and columns. The bank of standard array cells (12) includes a plurality of rows of array cells (14) operable to provide memory storage and a plurality of rows of dummy cells (16) operable to provide a reference voltage level. A row decode block (22) is coupled to the bank of standard array cells via a plurality of wordlines (18) which include array cell wordlines and dummy cell wordlines. A sense amplifier block (24) is coupled to the bank of standard array cells (12) via a plurality of bitlines (20). The sense amplifier block (24) includes a plurality of sense amplifiers (26) coupled to the bitlines. The memory array (10) is operable to charge the plurality of dummy cells (16) to a precharge voltage level during a bitline (20) precharge period such that the dummy cells (16) operate to provide a reference voltage and capacitive balance to the sense amplifiers (26) when sensing an array cell (14).


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