The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 1998
Filed:
Apr. 04, 1997
Joseph Hani Hassoun, Pleasanton, CA (US);
James A Gasbarro, Mountain View, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Rambus, Inc., Mountain View, CA (US);
Abstract
A test device for an integrated circuit utilizes current mode test signal shaping to evaluate circuit performance within at least one selected voltage swing. An interface circuit has an output line that is coupled to the integrated circuit under test. An upper voltage level (V.sub.OH) is established by a connection of the output line to a voltage source. The connection to the source includes a resistor. Parallel switchable current paths to a voltage level significantly less than V.sub.OH are also formed from the output line. In the preferred embodiment, the current paths are MOS transistors to electrical ground. The transistors in an 'on' state act as current sinks that create a greater voltage drop across the resistor. Consequently, there is a correspondence between the number of transistors that are switched by input of a test signal and the difference between V.sub.OH and V.sub.OL. In the preferred embodiment, the interface circuit is used in the testing of a memory circuit, such as DRAM. Test sequences can be executed at different levels of V.sub.OH and V.sub.OL, thereby ensuring that the integrated circuit under test will operate properly under different potential conditions.