Adjustable cell plate generator

Abstract

A dynamic random access memory device includes a plurality of dynamic memory cells. Each dynamic memory cell is formed at least in part by a cell plate which is connected to a normally fixed reference voltage. The reference voltage is produced by a cell plate generator. The cell plate generator has a first group of voltage divider transistors connected in series from an upper supply voltage source, and a second group of voltage divider transistors connected in series from a lower supply voltage source. The first and second groups of series-connected voltage divider elements form two intermediate voltage divider nodes which are connected to establish the reference voltage. The voltage divider elements are selected to normally establish the reference voltage at a nominal operating value. However, a first bypass transistor is connected around at least one of the voltage divider elements of the first group to selectively bypass it and to thereby raise the reference voltage to a first adjusted testing value which is greater than the nominal operating value. A second bypass transistor is connected around at least one of the voltage divider elements of the second group to selectively bypass it and to thereby lower the reference voltage to a second adjusted testing value which is lower than the nominal operating value.