The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 1998

Filed:

Apr. 02, 1996
Applicant:
Inventor:

Harish K Sarin, Fremont, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395500 ;
Abstract

A method for accurately and efficiently simulating power behavior of digital VLSI MOS circuit at the gate-level. The method characterizes both the static and dynamic power consumed by a cell for different logic state conditions on all its ports. For each state-vector, power-consumption measurements are carried out for different conditions of input ramp and output load. The method looks at the power behavior of each state-vector for different values of input ramp and output loads as allowed by the technology of that cell. The exhibited power behavior is then modeled in terms of power-coefficients of the power dissipation model. These power-coefficients, which are determined by the characterizer, provide a mechanism to capture the different power consumption dependencies under varying state-vector conditions, input ramp, and output load for different types of cells. The model is unique as it has the same form for all cells, but its coefficients are customizable for each power vs. input-ramp vs. output load dependency, thereby allowing the exact modeling of the complexities exhibited by the power behavior of different state-vectors for the different cells. These coefficients are used during simulation to compute the power consumed by the cell under the applicable state-vector and circuit-conditions to which each cell instance is subjected in the circuit.


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