State dependent power modeling

Abstract

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular pin (e.g., input, output, bidirectional, internal) based on a prescribed condition of the state of signals that exist contemporaneously with a signal transition on the particular pin. This is referred to as state dependent power modeling. A different power consumption value can be provided for each different modeled state. The logic cells and the power consumption model for them are stored in a logic cell 'library' within the computer system. State dependent power modeling of the present invention allows library designers to specify a different set of power values depending on the condition of one or more pins of the library cell (e.g., the library's representation of the logic cell). Specifically, library designers are allowed to specify a 'when' condition with their power tables. To take advantage of the state dependent power modeling, library designers can specify multiple power tables in the library cell with different when conditions. State dependent power modeling is important for those cells for which a certain condition of the pins makes the logic cell consume more or less power than the otherwise recorded 'average' power rating used in conventional libraries. Examples of these cells are random access memories (RAMs), input/output cells (IOs), and enabled flip-flops.