Photolithographic process for mask programming of read-only memory

Abstract

A photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. The photolithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks. In the first exposure process, a first selected set of areas on the photoresist layer is exposed through the photomask. In the second exposure process, the photomask is shifted to predetermined positions interleaving or overlapping the positions where the first selected set of exposed areas are formed, or alternatively a second photomask replaces the first photomask. The second photomask has a plurality of patterns arranged in positions correspondingly interleaving or overlapping the positions where the first selected set of exposed areas is formed. The exposure light then illuminates the wafer again so as to expose a second selected set of areas on the photoresist layer. The first and second selected sets of exposed areas in combination constitute a layout for the circuit elements which are to be subsequently formed. Through the photolithographic process, the circuit elements are doubled in density compared with the corresponding patterns on the photomask and can be formed with a reduced line width or inter-element space.